View HI-1575PCIF_5171855.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

holt integrated circuits www.holtic.com hi-1575 mil-std-1553 3.3v dual transceivers with integrated encoder / decoders description features pin configurations the hi-1575 is a low power cmos dual transceiver with on-chip manchester ii encoder and dual decoder designed to meet the requirements of the mil-std-1553 specification. the part acts as a "smart transceiver", allowing users to transmit and receive properly encoded mil-std-1553 command and data words between a 16-bit host processor and dual mil-std-1553 data buses. a single write cycle is used to transfer a word to the hi-1575, which encodes the data, adds the selected sync and parity bits, and transmits the word on the chosen mil-std-1553 data bus. complete mil-std-1553 messages may be transmitted by executing multiple write cycles to the device. activity on both mil-std-1553 data buses is continuously monitored. when the hi-1575 detects a properly encoded word, a hardware interrupt is generated and the information is decoded and stored in one of two internal registers, which may then be read by the host processor. bits in the internal status & mode register indicate on which bus the word was received and whether the word had a data or command sync. compliant to mil-std-1553a & b 3.3v single supply operation on-chip encoder and dual decoder small footprint available in 32-pin plastic tqfp package less than 0.5w maximum power dissipation 6 mm x 6 mm 40-pin plastic chip-scale package option military processing options february 2006 (ds1575 rev.b) 02/06 pin configurations 40 - 39 38 37 36 d0 35 d1 34 d2 33 d3 32 d4 31 - error /chb clk cha -1 rcva 2 3 busa 4 vdd 5 6 busb 7 rcvb 8 reg 9 -10 busa busb 30 - 29 d5 28 d6 27 d7 26 gnd 25 d8 24 d9 23 d10 22 d11 21 - -11 r/ 12 13 mr 14 sync 15 d15 16 d14 17 d13 18 d12 19 -20 w strb 1575pci 1575pct 40 pin plastic 6mm x 6mm chip-scale package 32 pin tqfp package 24 - d5 23 - d6 22 - d7 21 - gnd 20 - d8 19 - d9 18 - d10 17 - d11 rcva - 1 -2 busa - 3 vdd - 4 -5 busb - 6 rcvb - 7 reg - 8 busa busb r/ - 9 -10 mr - 11 sync - 12 d15 - 13 d14 - 14 d13 - 15 d12 - 16 w strb 32 - error 31 - /chb 30 - clk 29 - d0 28 - d1 27 - d2 26 - d3 25 - d4 cha hi-1575pqi & hi-1575pqt
holt integrated circuits 2 pin symbol function pull-up description (tqfp) pull-down 1 rcva digital output - goes high when mil-std-1553 word received on bus a 2 3 4 5, 6 7 8 reg busa busb w strb cha analog i/o - mil-std-1533 bus driver a, negative signal busa analog i/o - mil-std-1553 bus driver a, positive signal vdd power supply - +3.3 vdcr analog i/o - mil-std-1533 bus driver b, negative signal busb analog i/o - mil-std-1553 bus driver b, positive signal rcvb digital output - goes high when mil-std-1553 word received on bus b digital input 12k pull-down selects status & mode register when high, or data registers when low 9 r/ digital input 12k pull-up controls data and sync direction during read or write operations 10 digital input 12k pull-up strobe. timing input to control register read and write operations 11 mr digital input 12k pull-down pulse high to reset the hi-1575 12 sync digital i/o 12k pull-down selects transmit sync type on write, indicates received sync type on read. 13-20, 22-29 d15:d0 digital i/o 12k pull-down data bus. d15 (msb) corresponds to mil-std-1553 bit 4 21 gnd power supply - ground 30 clk digital input - 12 mhz clock 31 /chb digital input 12k pull-down selects mil-std-1553 bus a or bus b 32 error digital output - goes high when a received mil-std-1553 word has an encoding error pin descriptions functional description figure 1 shows a simplified block diagram of the hi-1575. the mr (master reset) input should be pulsed high to initialize the manchester ii encoder and decoders. mr also clears the receive data registers, rxa and rxb, and sets the status & mode register to its default state as described in figure 2. the clk input requires a 12.0 mhz clock signal. clk is used to derive the 1.0 us bit period for mil-std-1553 data transmission, as well to provide the master clock for the manchester ii encoder and the decoder's receiver sampling logic. the hi-1575 is configured by writing bits 0 - 5 of the sta- tus & mode (sam) register. refer to figure 2 for a com- plete description. sam bits 0 - 5 are read/write allowing the user to verify the chip's configuration at any time by reading the sam. sam is accessed by performing a read or write cycle with the reg input high. sam bits 6 - 15 are read-only and are used to provide status information. to allow the user to minimize the number of hardware control inputs, sam bit 5 (channel a/b select) is logically 'or'ed with the /chb input pin. to select between mil-std-1553 bus a or b, the user may either tie the /chb pin low and select buses using sam bit 5 (software control), or program sam bit 5 to a zero and use the /chb pin to select the active bus (hardware control). status & mode register cha cha cha similarly, the sync i/o pin may be left open-circuit al- lowing the transmitter sync to be programmed into sam bit 4, or sam bit 4 can be set to zero and the sync pin used to set the transmitted sync type. note that sync is an i/o pin. it is an input when writing data to the hi-1575 transmit data register (tx), and an output when reading data from the hi-1575 receivers (rxa and rxb). the sync pin must not be shorted directly to vdd or gnd. an internal pull-down resistor allow the sync pin to be left open-circuit if the user opts for purely software control. data words to be transmitted on the mil-std-1553 data bus are written to the tx register by pulsing low while r/ is low and reg is low. the logical or of the /chb input pin and sam bit 5 (chan) during the write cycle determines whether the word is output on mil-std-1553 bus a or b. setting /chb or chan to a zero selects bus a, and a one selects bus b. the log- ical or of the sync pin and sam bit 4 (txsync) dur- ing the write cycle defines whether the transmitted word is a mil-std-1553 command or data word. setting sync to a one causes a command (or status) sync to be generated. setting sync to zero selects a data sync. note that the sync pin is bidirectional. it should be treated as an extension to the 16-bit bidirectional databus (d15:d0) in terms of i/o switching and timing. the hi-1575 automatically calculates and appends the cor- rect parity bit to the transmitted word. each word is as- signed odd parity as required by mil-std-1553. transmitter strb w cha cha hi-1575
hi-1575 holt integrated circuits 3 clk decoder a 6 5 3 2 4 30 10 9 31 13-20, 22-29 1 decoder b encoder shift tx shift status & mode strb r/w cha/chb sync rxa databus vdd rcva rxb shift 21 gnd figure 1. hi-1575 block diagram to transmit contiguous words, a second write to the tx register must occur no earlier than 3.5 us and no later than 18.5 us after the first tx write. sam bit 15 (senddata) is high during this period and may be used as a flag to indicate when the hi-1575 is ready to accept the next data write for contiguous transmission. when transmitting a message of three or more words, the third and subsequent write operations should occur every 20.0 us so as to avoid over-writing the previous data before it is transferred to the transmitter's shift register. figure 3 shows a timing diagram for transmit operations. the transmitter outputs are either direct or transformer coupled to the mil-std-1553 data bus. both coupling methods produce a nominal voltage on the main mil-std-1553 bus of 7.5 volts peak-to-peak, line-to-line. figure 6 shows bus coupling examples. one or both transmitters may be disabled by writing a '1' into sam register bits 0 or 1 (txdisa, txdisb). when dis- abled, the host interface works as normal, but there is no output from the busa and (busb and ) pins. busa busb receiver the hi-1575's two receivers continuously monitor both mil-std-1553 data busses. bi-phase differential data words are accepted from the mil-std-1553 bus through the same direct or transformer coupled interface as the transmitter. each receiver?s differential input stage drives a filter and threshold comparator that presents data to the decoders. the decoder logic checks the incoming word for correct encoding, bit count and parity. if a valid mil-std-1553 word is received, the rcva or rcvb output goes high and the 16-bit received word is transferred to the rxa or rxb register. the hi-1575 error output goes high whenever an encoding error is detected on either bus. if a received word has an encoding error, then sam bits 10 or 14 (errora, errorb) are set high, and the corresponding rcva or rcvb pin is not asserted. to minimize the number of pins necessary to interface the hi-1575, the state of rcva and rcvb can also be read from sam bits 7 and 11. holt integrated circuits 3 7 rcvb 11 mr busa busa busb busb 12 error 32 6 10
hi-1575 figure 2. status and mode register bit name 0 txdisa r/w 0 writing txdisa to a '1' disables the transmitter for mil-std-1553 bus a 1 txdisb r/w 0 writing txdisb to a '1' disables the transmitter for mil-std-1553 bus b 2 rena r/w 1 setting rena to a '1' enables the receiver for mil-std-1553 bus a. a '0' disables the receiver causing the hi-1575 to ignore all activity on bus a. 3 renb r/w 1 setting renb to a '1' enables the receiver for mil-std-1553 bus b. a '0' disables the receiver causing the hi-1575 to ignore all activity on bus b. 4 txsync r/w 0 the txsync bit is logically ored with the sync input pin during host write cycles to the transmit data register (tx). if txsync or sync is a '1' the transmitter prefixes the transmitted word with a mil-std-1553 command sync. if txsync or sync is a '0' during a write to tx, then the transmitted word has a mil-std-1553 data sync. 5 chan r/w 0 the chan bit is logically ored with the /chb input pin and the result used to select between mil-std-1553 bus a or b during write transfers to the tx register, or reading data from the rx registers. when chan or /chb is a '0' during a transmit operation, data is transmitted on mil-std-1553 bus a. when the result is a '1', mil-std-1553 bus b is selected. during hi-1575 data read cycles, if chan or /chb is a '0', the rxa register is accessed, and if chan or /chb is a '1' then the data is read from rxb. 6 - read-only 0 not used. internally set to '0'. 7 rcva read-only 0 this bit reflects the state of the rcva output pin. rcva goes high whenever a new word is received on mil-std-1553 bus a. the received word may be read by the host from the rxa register. rcva is reset on reading rxa or if the hi-1575 detects a new word arriving on bus a. if the data words are contiguous, then rcva will be high for about 3 us before the new word resets it. the data is still available in the rxa register and may be retreived any time up until the rcva flag goes high again. if the user does not read the data, the word is lost when the rcva flag goes high on reception of the next word. 8 rsynca read-only 0 rsynca indicates the sync of the last mil-std-1553 word received on bus a. rsynca is a '0' for a data sync, and a '1' for a command sync. when the rxa register is read, the rsynca value is also output on the sync i/o pin. 9 gapa read-only 0 gapa is a '1' when there is no activity detected on mil-std-1553 bus a, for example during an inter-message gap. gapa is a '0' whenever the hi-1575 detects bus traffic. 10 errora read-only 0 errora goes high when the hi-1575 manchester decoder receives an incorrectly encoded word on mil-std-1553 bus a 11 rcvb read-only 0 same function as rcva but for mil-std-1553 bus b. 12 rsyncb read-only 0 same function as rsynca but for mil-std-1553 bus b. 13 gapb read-only 0 same function as gapa but for mil-std-1553 bus b. 14 errorb read-only 0 same function as errora but for mil-std-1553 bus b. 15 senddata read-only 1 senddata goes high approximately 3.5 us after the start of a mil-std-1553 word transmission. sendata goes low approximately 18.5 us after the start of a mil-std-1553 word transmission. if new a new data word is written to the tx register while senddata is high, that word will be transmitted contiguously after the currently transmitting word. r/w default description cha cha cha cha 1514131211109876543210 msb lsb txsync renb rena txdisb txdisa chan not used holt integrated circuits 4 rcva rsynca gapa errora 0 rcvb rsyncb gapb errorb senddata status & mode register (sam)
15 14 13 3 2 1 0 p sync sync valid don?t care cha/chb r/w d15-d0 reg strb busa (b) figure 3. example transmit operation txdata don?t care don?t care don?t care 15 sync sync 15 14 13 12 2 1 0 p sync sync busa (b) rcva (b) don?t care cha/chb r/w reg strb don?t care don?t care 15 14 sync sync 13 12 valid d15-d0 sam rxa (b) figure 4. example receive operation hi-1575 holt integrated circuits 5 valid txdata sam 3 write tx, (mil-std-1553 status word) read sam, check senddata=1 write tx, (mil-std-1553 data word) sync don?t care sync sync read sam read rxa or rxb, (mil-std-1553 data word) 0 0 receiver a data (rxa) 1 0 receiver b data (rxb) x 1 status & mode register (sam) chan or /chb reg cha register figure 5. hi-1575 register map
holt integrated circuits 6 55 ohms cha/chb clk strb d15:d0 r/w reg busa busa mil-std-1553 bus b (transformer coupled) 1:2.5 52.5 ohms rcva gnd busb busb 1:2.5 1:1.4 mil-std-1553 bus a (direct coupled) 3.3 v vdd hi-1575 hi-1575 55 ohms 52.5 ohms host cpu 12.0 mhz mil-std-1553 bus connection the hi-1575 includes on-chip mil-std-1553 analog transceivers which are designed to drive the primary winding of a 1:2.5 turns-ratio mil-std-1553 isolation transformer. figure 6 shows how the hi-1575 may be connected to the mil-std-1553 data bus as either a direct coupled stub (bus a example), or a transformer coupled stub (bus b example). holt integrated circuits offers a wide range of single-core and dual-core coupling transformers suitable for use with the hi-1575. figure 6. mil-std-1553 bus connection rcvb mr error sync the host reads the received word from the hi-1575 rxa or rxb register. the data word is read by pulsing low, while r/ is high and reg is low. figure 4 shows an example receive operation. the sync output indicates whether the word had a command sync (sync=1) or data sync (sync=0). sam register bits 8 and 12 (rsynca and rsyncb) retain the sync values for the last word received on each bus. sam bits 2 or 3 (rena, renb) can be used to independently enable or disable each receiver. writing a '1' to rena enables receiver a. a '0' disables the receiver. renb performs the same function for the mil-std-1553 bus b. note that because each receiver is internally connected to its transmitter, when a mil-std-1553 word is transmitted by the hi-1575 it will also be received on the same channel. this feature allows the terminal to self-monitor data transmitted to the mil-std-1553 data bus. strb w figure 7. mil-std-1553 word formats 123456789 10 11 13 12 14 15 16 17 18 19 20 bit period command word data word status word r/t subaddress / mode data word count p p p data word terminal address me code for failure modes terminal address sync sync sync sync sync sync tf
holt integrated circuits 7 timing diagrams figure 8. mil-std-1553 bus receiver timing bit period bit period bit period busa - (busb - ) busa busb t r1 t r2 t r3 zero one one command sync data sync busa - (busb - ) busa busb busa - (busb - ) busa busb t r1 t r1 t r1 t r2 t r2 t r3 hi-1575 t fh mid-parity 1553 bus rcva(b) error strb data word with error command mid-parity mid-sync mid-sync mid-parity mid-sync figure 9. hi-1575 receiver timing (read rxa) (read rxa) (read sam) valid figure 10. databus timing - write. t rws t rwh t chwh t dwh t dws t chws t rwwh t rwws reg valid d15:0 sync cha/chb strb r/w t str reg t rrs valid t rrh t chrh t drt t drv t chrs figure 11. databus timing - read d15:0 sync cha/chb strb r/w t rwrh t rwrs t str valid t fh t fh t fr t fr t fr t rf t rf t rf
dc electrical characteristics absolute maximum ratings recommended operating conditions note: stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. these are stress ratings only. operation at the limits is not recommended. supply voltage ( logic input voltage range power dissipation at 25c 1.0 w solder temperature 275c for 10 sec. junction temperature 175c storage temperature -65c to +150c vdd) -0.3 v to +5 v -0.3 v dc to +3.6 v receiver differential voltage +/- 10 vp-p driver peak output current +1.0 a vdd = 3.3 v, gnd = 0v, t = operating temperature range (unless otherwise specified). a supply voltage temperature range industrial screening.........-40c to +85c hi-temp screening........-55c to +125c vdd....................................... 3.3v... 5% hi-1575 output voltage direct coupled 35 ohm load 6.0 9.0 vp-p (measured at point ?a ? in figure 12) 70 18.0 27.0 vp-p output noise v differential, inhibited 10.0 mvp-p output dynamic offset voltage v -90 90 mv -250 250 mv output resistance r differential, not transmitting 10 kohm transmitter(measured at point ?a ? in figure 12 unless otherwise specified) d d on dyn out v transformer coupled v ohm load (measured at point ?a ? in figure 13) direct coupled 35 ohm load (measured at point ?a ? in figure 12) transformer coupled v 70 ohm load (measured at point ?a ? in figure 13) out out t d dyn t holt integrated circuits 8 parameter symbol condition min typ max units operating voltage v 3.15 3.30 3.45 v total supply current i not transmitting 4 10 ma i transmit one channel @ 225 250 ma 50% duty cycle i transmit one channel @ 0ma 100% duty cycle power dissipation p not transmitting 0.06 w p transmit one channel @ 0.3 0.5 w 100% duty cycle min. input voltage (hi) v digital inputs 70% v max. input voltage (lo) v digital inputs 30% v min. input current (hi) i digital inputs (without pull-down) 20 a max. input current (lo) i digital inputs (without pull-up) -20 a pull-up / pull-down current i digital inputs and data bus 275 ua min. output voltage (hi) v i = -1.0ma, digital outputs 90% v max. output voltage (lo) v i = 1.0ma, digital outputs 10% v input resistance r differential 20 kohm input capacitance c differential 5 pf common mode rejection ratio c 40 db input level v differential 9 vp-p input common mode voltage v -5.0 5.0 v-pk threshold voltage - direct-coupled detect 1.15 no detect 0.28 theshold voltage - detect 0.86 no detect 0.20 dd cc1 cc2 cc3 d1 d2 ih il ih il pud oh out ih out d in in mrr in icm 425 50 v 1 mhz sine wave vp-p v (measured at point ?a ? in figure 12) vp-p transformer-coupled v 1 mhz sine wave vp-p v (measured at point ?a ? in figure 13) vp-p dd dd dd dd receiver (measured at point ?a ? in figure 12 unless otherwise specified) thd thnd d thd thnd t
vdd = 3.3 v, gnd = 0v, t =operating temperature range (unless otherwise specified) a ac electrical characteristics holt integrated circuits 9 hi-1575 figure 12. direct coupled test circuits isolation transformer point ?a ? d hi-1575 transmitter hi-1575 receiver 1:2.5 55 55 35 2.5:1 55 55 35 busa/b busa/b isolation transformer point ?a ? d parameter symbol test conditions min typ max units risettime tr 35 ohm load 100 300 ns fall time tf 35 ohm load 100 300 ns receiver (see figures 8 and 9) sync transition span t 1500 ns short data transition span t 500 ns long data transition span t 1000 ns delay mid-parity to flag set t 2500 ns flag setup time to read t 0 ns flag reset delay t 60 ns data bus timing - write (see figure 10) strobe pulse width t 50 ns reg write setup time t 50 ns reg write hold time t 10 ns databus / sync write setup time t 50 ns databus / sync write hold time t 10 ns cha/ write setup time t 50 ns cha/ write hold time t 10 ns r/ write setup time t 50 ns r/ write hold time t 10 ns data bus timing - read (see figure 11) strobe pulse width t 50 ns reg read setup time t 50 ns reg read hold time t 10 ns data read to databus valid t 60 ns data read to databus tri-state t 0 60 ns cha/ read setup time t 50 ns cha/ read hold time t 10 ns r/ read setup time t 50 ns r/ read hold time t 10 ns transmitter (measured at point ?a ? in figure 12) d r1 r2 r3 fh fr rf str rws rwh dws dwh chws chwh rwws rwwh str rrs rrh drv drt chrs chrh rwrs rwrh strb chb chb w w strb chb chb w w
holt integrated circuits 10 hi -1575 transmitter busa/b busa/b 52.5 (.75 zo) 52.5 (.75 zo) 2.5:1 1:2.5 1:1.4 1.4:1 35 (.5 zo) figure 13. transformer coupled test circuits coupling transformer coupling transformer isolation transformer isolation transformer hi-1575 receiver 52.5 (.75 zo) 52.5 (.75 zo) 35 (.5 zo) point ?a ? t point ?a ? t applications note holt applications note an-500 provides circuit design notes regarding the use of holt mil-std-1553 data communications devices. layout considerations, as well as recommended interface and protection components are included. heat sinking the leadless plastic chip carrier package the hi-1575pci/t is packaged in a 40 pin leadless plastic chip carrier (lpcc). this package has a metal heat sink pad on its bottom surface, which should be soldered to the printed circuit board for optimum thermal dissipation. the package heat sink is electrically isolated and may be soldered to any convenient power plane or ground plane. redundant "vias" between the exposed board surface and buried power or ground plane will enhance thermal conductivity. hi-1575
holt integrated circuits 11 hi-1575 part number package style condition junction temperature hi-1575pci / t 32 pin pqfp 40 pin lpcc heat sink pad soldered mounted on circuit board hi-1575pqi / t 59.5 c / w 27.5 c / w tbdc t = 25c a ja t = 85c a t = 125c a tbdc tbdc tbdc tbdc tbdc data taken at vdd = 3.3v, continuous data transmission at 1 mbit/s, single transmitter enabled. thermal characteristics ordering information package description temperature range 32 pin plastic pqfp 40 pin chip scale package (pcm not available) flow burn in -40c to +85c no i -55c to +125c -55c to +125c no yes t m hi - 1575 xx x x part number t m i part number pq pc part number lead finish 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank
package dimensions inches (millimeters) holt integrated circuits 12 heat sink stud on bottom of package. 6.00 .10 6.00 .10 4.65 .15 4.65 .15 0.40 .05 0.25 typ 0.50 0.2 typ 0.90 .10 40-pin plastic chip-scale package .3543 bsc (9.00 bsc) sq. .063 max. (1.60 max.) .0315 bsc (0.80 bsc) .0148 .0030 (0.375 .075) .0551 .002 (1.4 .05) .0031 r min. (0.08 r min.) .0039 .002 (0.10 .05) 0 7 .2755 bsc (7.00 bsc) sq. see detail a detail a .0055r .0024 (0.14r .06) .0236 .0059 (0.60 .15) package type: 32ptqs 32 pin plastic thin quad flat pack (pqfp) .00057 .00022 (0.0145 .0055) millimeters see detail a detail a 0.02 typ 0.90 .10

▲Up To Search▲

Price & Availability of HI-1575PCIF

	To Download HI-1575PCIF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .